In order to fabricate semiconductor devices with higher speed and lower power consumption, silicon based integrated circuits (ICs) or thin film transistors (TFTs), or the like (refer to patent document 1) are required featuring a low RC delay interconnection pattern (refer to non-patent document 1 below). Examples of such a semiconductor devices may include high-speed central processing units (CPUs) or large-size liquid crystal display (LCD) devices. Further, in silicon based ultra large integration (ULSI) systems, interconnections with low electrical resistivity are required to increase their integration density even though they may include interconnection with small width. In addition, in order to fabricate semiconductor devices with higher reliability, interconnections made from materials which are superior in electro-migration (EM) and stress-migration (SM) resistance are required (refer to patent document 1 below).
[Patent document 1] Japanese unexamined patent application no. H11-186273
[Non-Patent Document 1] “Semiconductor Device (2nd edition)—Physics and Technology” by S. M. Sze (Oct. 5, 2005, Sangyo Tosho, Co., Ltd., third impression of second edition, P345-346.
To achieve the aforementioned needs, a technique is disclosed to form interconnections for the semiconductor devices described above using copper (Cu) as an interconnection body. Copper has a lower resistivity compared to aluminum (Al) or an aluminum alloy, such as aluminum copper silicon (AlCuSi) alloy, and is superior in electro-migration EM resistance (refer to patent document 1 above and patent documents 2-6 below). For example, a technique is disclosed to form a damascene type interconnection structure having an interconnection body made of copper formed on an insulating layer containing silicon, such as SiO2, through a diffusion barrier layer, thereby preventing copper from diffusing into the insulating layer (refer to patent documents 7 and 8 below).
[Patent document 2] Japanese unexamined patent application publication no. S63-156341
[Patent document 3] Japanese unexamined patent application publication no. H01-202841
[Patent document 4] Japanese unexamined patent application publication no. H05-047760
[Patent document 5] Japanese unexamined patent application publication no. H06-140398
[Patent document 6] Japanese unexamined patent application publication no. H06-310509
[Patent document 7] Japanese unexamined patent application publication no. H11-054458
[Patent document 8] Japanese unexamined patent application publication no. H11-087349
In the above mentioned copper interconnection, the diffusion barrier layer has conventionally been made from manganese (Mn) (refer to patent document 5 above and patent documents 9 and 10 below), or boride or nitride of manganese (Mn) (refer to patent document 5 above), tantalum (Ta) (refer to patent document 2 above), chromium (Cr) (refer to patent documents 2 and 3 above), titanium (Ti) (refer to patent document 3 above), titanium nitride (TiN) (refer to patent documents 1 and 2 above), tungsten (W) (refer to patent document 2 above), molybdenum (Mo) (refer to patent document 2 above), zirconium (Zr) (refer to patent document 3), vanadium (V) (refer to patent document 3 above), niobium (Nb) (refer to patent document 3 above), nitride film of Zr, Ti, V, Ta, Nb, Cr, or boron compound film (refer to patent document 3 above), and the like.
Also, a technique for forming a diffusion barrier layer from a multilayer structure has been disclosed (refer to patent document 6 above). The technique disclosed in the patent document 6 prevents copper from diffusing into the SiO2 insulating layer by providing a “trap layer” made of manganese (Mn) or magnesium (Mg) around the diffusion barrier layer, or as a base of the diffusion barrier layer which is made from tantalum (Ta), tungsten (W), or tantalum.tungsten (Ta—W) alloy.
Copper constituting the interconnection body is formed on the barrier layer by an electrolytic plating method, sputtering method (refer to patent documents 9 and 10 below), or plasma CVD (chemical vapor deposition) method (refer to patent document 11 below). As an example, a copper layer for an interconnection made of (111), (200), and (311) crystal faces is formed on a niobium (Nb) layer (refer to patent document 11 above). In order to uniformly form a copper interconnection body over a barrier layer, another technique is also disclosed where the copper interconnection body is formed through a seed layer, which is formed from a thin layer of copper (refer to patent document 12 below). For example, the copper layer of an interconnection formed by the electrolytic plating method over a thin layer of copper, which in turn is formed on a tantalum nitride (TaN) layer by a sputtering method, does not constitute a surface with uniform crystal face indexes. Instead, the surface is constituted from crystal faces with different indexes, such as (111), (200), and (311) crystal faces (refer to patent document 10).
[Patent document 9] Japanese unexamined patent application publication no. 2005-277390
[Patent document 10] Japanese unexamined patent application publication no. 2003-142487
[Patent document 11] Japanese unexamined patent application publication no. H05-190548
[Patent document 12] Japanese unexamined patent application publication no. 2006-049641
In recent years, another technique has been disclosed in that, rather than forming separately a barrier layer from tantalum or tantalum nitride and a copper seed layer over the barrier layer for forming the copper interconnection body, forming both of the above layers in a self forming manner (refer to patent document 9 above and patent document 13 below). For example, a technique has been known to form a diffusion barrier layer, in which its surface layer is a layer mainly composed of copper. The diffusion barrier layer is formed from a copper alloy layer with an alloying metal element and is formed on an insulating layer containing silicon (refer to patent documents 9 above, and patent document 13 below).
[Patent document 13] Japanese patent no. 4065959
According to the above mentioned technique, the copper interconnection body may easily be structured using the layer mainly composed of copper formed on the surface portion of the diffusion barrier layer. In this technique, the layer mainly composed of copper is used as a copper seed layer for forming the diffusion barrier layer in a self forming manner. Examples of the metal alloying element in the copper alloy layer may include manganese (Mn), niobium (Nb), zirconium (Zr), chromium (Cr), vanadium (V), yttrium (Y), rhenium (Re) and the like (refer to patent document 9 above).
The metal element described above has a diffusion coefficient greater than the self diffusion coefficient of copper and the metal element is oxidized more easily compared to copper (refer to patent document 13). In order to form a diffusion barrier layer in a self forming manner from a copper alloy layer or a solid solution layer containing the above mentioned metal elements as a material, it is common to conduct heat treatment on the copper alloy layer or the solid solution layer, after depositing these layers on an insulating layer (refer to patent documents 9 and 13 above).
An advantage of using the copper alloy or solid solution layers containing a metal element having a diffusion coefficient greater than the self diffusion coefficient of copper and being oxidized more easily compared to copper, is that the diffusion barrier layer, in which its surface layer is mainly composed of copper (copper seed layer), may be formed in a self forming manner by conducting the heat treatment. Meanwhile, however, there has been a problem in that the surface layer of the diffusion barrier layer, which is mainly composed of copper, is made from various crystallographic faces (crystal face) when the diffusion barrier layer is formed by heating the copper alloy layer or the solid solution layer containing such additive elements.
A concrete example of such a technical disadvantage resulted from the above mentioned problem is the possibility of providing a copper interconnection with a large amount of crystal grain boundaries on the surface layer of the diffusion barrier layer which is mainly composed of copper. When a large amount of crystal grain boundaries are present in the copper interconnection, the diffusion of copper constituting the interconnection body through the grain boundaries occurs significantly, thereby electro-migration (EM) resistance and stress-migration (SM) resistance are decreased. Further, the insulating property of the insulating layer is decreased for a damascene type copper interconnection structure. Therefore, the achievement of semiconductor devices with high operating reliability has not yet been met.
The present invention is made under the above-mentioned situation. The purpose of the present invention is to provide copper interconnection structures with low electrical resistance and with improved electro-migration (EM) and stress-migration (SM) resistance.